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mitsubishi electric - 1 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric description M2S12D20TP is a 4 - bank x 33,554,432 - word x 4 - bit, m2s12d30tp is a 4 - bank x 16,777,216 - word x 8 - bit, double data rate synchronous dram, with sstl_2 interface. all co ntrol and address signals are referenced to the rising edge of clk. input data is registered on both edges of data strobes, and output data and data strobe are referenced on both edges of clk . the m2s12d20/30tp achieve very high speed data rate up to 133mhz, and are suitable for mai n memory in computer systems. features - vdd=vddq=2.5v + 0.2v - double data rate architecture; two data transfers per clock cyc le - bidirectional, data strobe (dqs) is transmitted/received with d ata - differential clock inputs (clk and /clk) - dll aligns dq and dqs transitions - commands are entered on each positive clk edge; - data and data mask are referenced to both edges of dqs - 4 bank operations are controlled by ba0, ba1 (bank address) - /cas latency - 2.0/2.5 (programmable) - burst length - 2/4/8 (programmable) - burst type - sequential / interleave (programmable) - auto precharge / all bank precharge is controlled by a10 - 8192 refresh cycles /64ms (4 banks concurrent refresh) - auto refresh and self refresh - row address a0 - 12 / column address a0 - 9,11 - 12(x4)/ a0 - 9,11(x8) sstl_2 interface - 400 - mil, 66 - pin thin small outline package (tsop ii) - jedec standard - low power for the self refresh current icc6 :4ma ( - 75l, - 10l) 125 mhz 100 mhz - 10 / - 10 l cl=2.5 * cl=2 * 133 mhz 100 mhz - 75 / - 75 l clock rate speed grade operating frequencies * cl = cas(read) latency contents are subject to change without notice.
mitsubishi electric - 2 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric clk,/clk : master clock cke : clock enable / cs : chip select / ras : row address strobe / cas : column address strobe / we : write enable dq0 - 7 : data i/o dqs : data strobe dm : write mask vref : reference voltage 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 66 pin tsop(ii) 400 mil width x 875 mil length 0.65 mm lead pitch row a0 - 12 column a0 - 9,11 - 12(x4) a0 - 9,11 (x8) vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc nc vddq nc nc vdd nc nc / we / cas / ras / cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc nc vssq dqs nc vref vss dm / clk clk cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss a0 - 12 : address input ba0,1 : bank address input vdd : power supply vddq : power supply for output vss : ground vssq : ground for output vss nc vssq nc dq3 vddq nc nc vssq nc dq2 vddq nc nc vssq dqs nc vref vss dm / clk clk cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss vdd nc vddq nc dq0 vssq nc nc vddq nc dq1 vssq nc nc vddq nc nc vdd nc nc / we / cas / ras / cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd pin configuration(top view) x8 x4
mitsubishi electric - 3 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric pin function clk, /clk input clock: clk and /clk are differential clock inputs. all address a nd control input signals are sampled on the crossing of the positive edge o f clk and negative edge of /clk. output (read) data is referenced to the c rossings of clk and /clk (both directions of crossing). cke input clock enable: cke controls internal clock. when cke is low, inte rnal clock for the following cycle is ceased. cke is also used to select a uto / self refresh. after self refresh mode is started, cke becomes asynchronous inp ut. self refresh is maintained as long as cke is low. / cs input chip select: when /cs is high, any command means no operation. / ras, /cas, /we input combination of /ras, /cas, /we defines basic commands. a0 - 12 input a0 - 12 specify the row / column address in conjunction with ba0,1. the row address is specified by a0 - 12. the column address is specified by a0 - 9,11 - 12(x4) and a0 - 9,11(x8). a10 is also used to indicate precharge option. when a10 is high at a read / write command, an auto prec harge is performed. when a10 is high at a precharge command, all banks ar e precharged. ba0,1 input dq0 - 7(x8), dq0 - 3(x4) input / output dqs vdd, vss power supply power supply for the memory array and peripheral circuitry. vddq, vssq power supply vddq and vssq are supplied to the output buffers only. bank address: ba0,1 specifies one of four banks to which a comm and is applied. ba0,1 must be set with act, pre, read, write commands . data input/output: data bus data strobe: output pin during read operation, input during writ e operation. edge - aligned with read data, placed at the centered of write data to capture the write data. symbol type description dm input input data mask: dm is an input mask signal for write data. inpu t data is masked when dm is sampled high along with the input data during a write operations. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. input / output vref input sstl_2 reference voltage.
mitsubishi electric - 4 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric type designation code this rule is applied to only synchronous dram family. mitsubishi main designation speed grade 10: 125 mhz@cl=2.5,100mhz@cl=2.0 75: 133 mhz@cl=2.5 ,100mhz@cl=2.0 package type tp: tsop(ii) process generation (blank):1st gen. function reserved for future use organization 2 n 2: x4, 3: x8 ddr synchronous dram density 12: 512m bits interface v:lvttl, s:sstl_3, _2 memory style (dram) m 2 s 12 d 3 0 tp ? 75 l block diagram / cs / ras / cas / we dm memory array bank #0 dq0 - 7 i/o buffer memory array bank #1 memory array bank #2 memory array bank #3 mode register control circuitry address buffer a0 - 12 ba0,1 clock buffer clk cke control signal buffer qs buffer dqs dll / clk power grade l:low power, (blank):standard
mitsubishi electric - 5 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric basic functions the m2s12d20/30tp provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. each command is defined by c ontrol signals of /ras, /cas and /we at clk rising edge. in addition to 3 signals, /cs ,cke and a 10 are used as chip select, refresh option, and precharge option, respectively. refer to the command truth table for the detailed definition of commands. / cs chip select : l=select, h=deselect / ras command / cas command / we command cke refresh option @refresh command a10 precharge option @precharge or read/write command clk define basic commands / clk activate (act) [/ras =l, /cas =/we =h] act command activates one row in an idle bank indicated by ba. read (read) [/ras =h, /cas =l, /we =h] read command starts burst read from the active bank indicated by ba. first output data appears after /cas latency. when a10 =h in this command, the bank is deactiva ted after the burst read (auto - precharge, reada ) write (write) [/ras =h, /cas =/we =l] write command starts burst write to the active bank indicated by ba. total data length to be written is defined by burst length. when a10 =h in this command, the ba nk is deactivated after the burst write (auto - precharge, writea ) precharge (pre) [/ras =l, /cas =h, /we =l] pre command deactivates the active bank indicated by ba. this co mmand also terminates burst read /write operation. when a10 =h in this command, all banks are dea ctivated (precharge all, prea ). auto - refresh (refa) [/ras =/cas =l, /we =cke =h] refa command starts auto - refresh cycle. refresh addresses including bank address are gene rated internally. after this command, the banks are precharged automat ically.
mitsubishi electric - 6 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric command truth table h=high level, l=low level, v=valid, x=don't care, n=clk cycle nu mber note: 1. applies only to read bursts while autoprecharge is disabled; thi s command is undefined (and should not be used) during read bursts while autoprecharge is enabled, as well as writ e bursts. 2. ba0 - ba1 select either the base or the extended mode register (ba0 = 0, ba1 = 0 selects mode register;ba0=1 , ba1 = 0 selects extended mode register; other combinations of ba0 - ba1 are reserved; a0 - a12 provide the op - codes to be written to the selected mode register. command mnemonic cke n - 1 cke n / cs / ras / cas / we ba0,1 a10 / ap a0 - 9, 11 - 12 deselect desel h x h x x x x x x no operation nop h x l h h h x x x row address entry & bank activate act h h l l h h v v v single bank precharge pre h h l l h l v l x precharge all banks prea h h l l h l h x column address entry & write write h h l h l l v l v column address entry & write with auto - precharge writea h h l h l l v h v column address entry & read read h h l h l h v l v column address entry & read with auto - precharge reada h h l h l h v h v auto - refresh refa h h l l l h x x x self - refresh entry refs h l l l l h x x x self - refresh exit refsx l h h x x x x x x l h l h h h x x x burst terminate term h h l h h l x x x mode register set mrs h h l l l l l l v x note 1 2
mitsubishi electric - 7 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric function truth table current state /cs /ras /cas /we address command action notes idle h x x x x desel nop l h h h x nop nop l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act bank active, latch ra l l h l ba, a10 pre / prea nop 4 l l l h x refa auto-refresh 5 l l l l op-code, mode- add mrs mode register set 5 row active h x x x x desel nop l h h h x nop nop l h h l ba term nop l h l h ba, ca, a10 read / reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write / writea begin write, latch ca, determine auto-precharge l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea precharge / precharge all l l l h x refa illegal l l l l op-code, mode- add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin new read, determine auto- precharge 3 l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode- add mrs illegal read(auto- precharge disabled)
mitsubishi electric - 8 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric function truth table (continued) current state /cs /ras /cas /we address command action notes h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin read, determine auto-precharge 3 l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto-precharge 3 l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode- add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada illegal for same bank 6 l h l l ba, ca, a10 write / writea illegal for same bank 6 l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea precharge / illegal 2 l l l h x refa illegal l l l l op-code, mode- add mrs illegal h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada illegal for same bank 7 l h l l ba, ca, a10 write / writea illegal for same bank 7 l l h h ba, ra act bank active / illegal 2 l l h l ba, a10 pre / prea precharge / illegal 2 l l l h x refa illegal l l l l op-code, mode- add mrs illegal write(auto- precharge disabled) read with auto-precharge write with auto-precharge
mitsubishi electric - 9 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric function truth table (continued) current state /cs /ras /cas /we address command action notes h x x x x desel nop (idle after trp) l h h h x nop nop (idle after trp) l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre / prea nop (idle after trp) 4 l l l h x refa illegal l l l l op-code, mode- add mrs illegal h x x x x desel nop (row active after trcd) l h h h x nop nop (row active after trcd) l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre / prea illegal 2 l l l h x refa illegal l l l l op-code, mode- add mrs illegal h x x x x desel nop l h h h x nop nop l h h l ba term illegal 2 l h l x ba, ca, a10 read / write illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre / prea illegal 2 l l l h x refa illegal l l l l op-code, mode- add mrs illegal row activating write re- covering pre- charging
mitsubishi electric - 10 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric function truth table (continued) abbreviations: h=high level, l=low level, x=don't care ba=bank address, ra=row address, ca=column address, nop=no opera tion notes: 1. all entries are valid only when cke was high during the prec eding clock cycle and the current clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of specific bank. 3. must satisfy bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba. 5. illegal if any bank is not idle. 6. refer to read with auto - precharge in page 23. 7. refer to write with auto - precharge in page 25. illegal = device operation and/or data - integrity are not guaranteed. current state /cs /ras /cas /we address command action notes refreshing h x x x x desel nop (idle after trc) l h h h x nop nop (idle after trc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode- add mrs illegal h x x x x desel nop (row active after trsc) l h h h x nop nop (row active after trsc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode- add mrs illegal mode register setting
mitsubishi electric - 11 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric function truth table for cke abbreviations: h=high level, l=low level, x=don't care notes: 1. low to high transition of cke re - enable clk and other inputs asynchronously. a minimum setup time must be satisfied before any command ex cept exit. 2. power - down and self - refresh can be entered only from the all banks idle state. 3. must be legal command. current state cke n-1 cke n /cs /ras /cas /we address action notes h x x x x x x invalid 1 l h h x x x x exit self-refresh (idle after trc) 1 l h l h h h x exit self-refresh (idle after trc) 1 l h l h h l x illegal 1 l h l h l x x illegal 1 l h l l x x x illegal 1 l l x x x x x nop (maintain self-refresh) 1 h x x x x x x invalid l h x x x x x exit power down to idle l l x x x x x nop (maintain self-refresh) h h x x x x x refer to function truth table 2 h l l l l h x enter self-refresh 2 h l h x x x x enter power down 2 h l l h h h x enter power down 2 h l l h h l x illegal 2 h l l h l x x illegal 2 h l l l x x x illegal 2 l x x x x x x refer to current state =power down 2 h h x x x x x refer to function truth table h l x x x x x begin clk suspend at next cycle 3 l h x x x x x exit clk suspend at next cycle 3 l l x x x x x maintain clk suspend any state other than listed above self- refreshing power down all banks idle
mitsubishi electric - 12 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric simplified state diagram row active idle pre charge power down read reada write writea power on act refa refs refsx ckel ckeh mrs ckeh ckel write read writea writea reada read pre reada reada pre pre prea power applied mode register set self refresh auto refresh active power down automatic sequence command sequence write read pre charge all mrs burst stop term
mitsubishi electric - 13 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric power on sequence the following power on sequences are necessary to guarantee t he proper operations of the ddr sdram. 1. apply vdd before or at the same time as vddq 2. apply vddq before or at the same time as vtt & vref 3. maintain stable conditions for 200us after stable power and c lk are supplied, assert nop or dsel 4. issue precharge command for all banks of the device 5. issue emrs to program proper functions 6. issue mrs to configure the mode register and to reset the dll 7. issue 2 or more auto refresh commands 8. maintain stable conditions for 200 cycle after these sequence, the ddr sdram is in the idle state and rea dy for normal operation. mode register burst length, burst type and /cas latency can be programmed by configuring the mode register (mrs). the mode register stores these data until the next mrs command, which may be issued when both banks are in idle state. after trsc from an mrs command, the ddr sdram is ready to accept the new command. / cs / ras / cas / we a12 - a0 / clk v clk ba0 ba1 r: reserved for future use 0 no 1 yes dll reset 0 sequential 1 interleaved burst type bt=0 bt=1 0 0 0 r r 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 r r 1 0 1 r r 1 1 0 r r 1 1 1 r r bl burst length /cas latency 0 0 0 r 0 0 1 r 0 1 0 2 0 1 1 r 1 0 0 r 1 0 1 r 1 1 0 2.5 1 1 1 r cl latency mode ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 0 0 dr 0 bt ltmode bl
mitsubishi electric - 14 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric extended mode register dll disable / enable mode can be programmed in setting the e xtended mode register (emrs). the extended mode register stores these d ata until the next emrs command, which may be issued when all banks are in idle state. after tmrd from a emrs command, the ddr sdram is ready to accept the new command. / cs / ras / cas / we a12 - a0 v ba0 ba1 / clk clk ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 0 0 0 0 0 0 0 0 0 0 0 ds dd 0 normal 1 weak drive strength 0 dll enable 1 dll disable dll disable
mitsubishi electric - 15 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric / cas latency burst length cl= 2 bl= 4 burst length a2 a1 a0 initial address bl sequential interleaved column addressing 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 - 0 0 - 0 1 - 1 0 - 1 1 - - 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0 2 3 0 1 3 0 0 1 7 6 5 4 0 1 2 3 1 0 3 2 2 3 0 1 3 2 0 1 - - 1 1 2 1 0 3 4 5 6 3 2 1 0 1 0 1 0 8 4 2 command address dq y y read write dqs q0 q1 q2 q3 d0 d1 d2 d3 / clk clk
mitsubishi electric - 16 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric absolute maximum ratings dc operating conditions ( ta=0 ~ 70 o c, unless otherwise noted) min. typ. max. vdd supply voltage 2.3 2.5 2.7 v vddq supply voltage for output 2.3 2.5 2.7 v vref input reference voltage 0.49*vddq 0.50*vddq 0.51*vddq v 5 vih(dc) high-level input voltage vref + 0.15 vddq+0.3 v vil(dc) low-level input voltage -0.3 vref - 0.15 v vin(dc) input voltage level, clk and /clk -0.3 vddq + 0.3 v vid(dc) input differential voltage, clk and /clk 0.36 vddq + 0.6 v 7 vtt i/o termination voltage vref - 0.04 vref + 0.04 v 6 notes limits symbol parameter unit symbol parameter conditions ratings unit vdd supply voltage with respect to vss -0.5 ~ 3.7 v vddq supply voltage for output with respect to vssq -0.5 ~ 3.7 v vi input voltage with respect to vss -0.5 ~ vdd+0.5 v vo output voltage with respect to vssq -0.5 ~ vddq+0.5 v io output current 50 ma pd power dissipation ta = 25 o c 1500 mw topr operating temperature 0 ~ 70 o c tstg storage temperature -65 ~ 150 o c ac overshoot/undershoot specification parameter specification maximum peak amplitude allowed for overshoot 1.6v maximum peak amplitude allowed for undershoot 1.6v the area between the overshoot signal and vdd must be less than or euqal to 4.5 v-ns the area between the undershoot signal and vss must be less than or euqal to 4.5 v-ns volts (v) 5 4 3 2 1 vss (0) - 1 - 2 - 3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 5.625 maximum amplitude overshoot undershoot maximum amplitude area (max.4.5v - ns) vdd time (ns)
mitsubishi electric - 17 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric average supply current from vdd ( ta=0 ~ 70 o c, vdd = vddq = 2.5v + 0.2v, vss = vssq = 0v, output open, unless otherwise noted) ac operating conditions and characteristics ( ta=0 ~ 70 o c, vdd = vddq = 2.5v + 0.2v, vss = vssq = 0v, output open, unless otherwise noted) min. max. vih(ac) high-level input voltage (ac) vref + 0.31 vil(ac) low-level input voltage (ac) vref - 0.31 vid(ac) input differential voltage, clk and /clk 0.7 vddq + 0.6 7 vix(ac) input crossing point voltage, clk and /clk 0.5*vddq - 0.2 0.5*vddq + 0.2 8 ioz off-state output current /q floating vo=0~vddq -5 5 m a ii input current / vin=0 ~ vddq -2 2 m a ioh output high current (vout = vtt+0.84v) -16.8 iol output high current (vout = vtt-0.84v) 16.8 ma ma notes limits v v v symbol parameter / test conditions unit v -75 -10 x4 140 130 x8 140 130 x4 150 140 x8 160 150 6 6 x4 30 25 x8 30 25 15 12 x4 45 35 x8 45 35 x4 190 140 x8 220 170 x4 180 150 x8 210 180 idd5 auto refresh current: t rc = t rfc (min) x4/x8 280 260 idd6 self refresh current: cke < 0.2v standard x4/x8 6 6 low power (-75l,-10l) x4/x8 4 4 x4 380 300 20 x8 400 320 20 idd0 idd1 operating current: one bank; active-read-precharge; burst = 2; t rc = t rc min; cl = 2.5; t ck = t ck min; iout= 0ma; address and control inputs changing once per clock cycle symbol organization parameter/test conditions operating current: one bank; active-precharge; t rc = t rc min; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle x4/x8 idd4r operating current: burst = 2; reads; continuous burst;one bank active; address and control inputs changing once per clock cycle;cl=2.5; t ck = t ck min; iout = 0 ma precharge power-down standby current: all banks idle; power- down mode; cke < vil (max); t ck = t ck min active standby current: /cs > vih (min); cke > vih (min); one bank; active-precharge; t rc = t ras max; t ck = t ck min; dq,dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle idd3n idd2p idd2f idle standby current: /cs > vih (min); all banks idle; cke > vih (min); t ck = t ck min; address and other control inputs changing once per clock cycle unit notes ma limits(max.) idd7 operating current-four bank operation: four bank interleaving with bl=4 -refer to the notes 20 idd4w operating current: burst = 2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; cl=2.5; t ck = t ck min;dq, dm and dqs inputs changing twice per clock cycle x4/x8 idd3p active power-down standby current: one bank active; power- down mode; cke < vil (max); t ck = t ck min
mitsubishi electric - 18 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric ac timing requirements ( ta=0 ~ 70 o c, vdd = vddq = 2.5v + 0.2v, vss = vssq = 0v, unless otherwise noted) min. max min. max tac dq output valid data delay time from clk//clk -0.75 0.75 -0.8 0.8 ns tdqsck dq output valid data delay time from clk//clk -0.75 0.75 -0.8 0.8 ns tch clk high level width 0.45 0.55 0.45 0.55 ns tcl clk low level width 0.45 0.55 0.45 0.55 ns cl=2.5 7.5 15 8 15 ns cl=2 10 15 10 15 ns tds input setup time (dq,dm) 0.5 0.6 ns tdh input hold time(dq,dm) 0.5 0.6 ns tdipw dq and dm input pulse width (for each input) 1.75 2 ns thz data-out-high impedance time from clk//clk -0.75 0.75 -0.8 0.8 ns 14 tlz data-out-low impedance time from clk//clk -0.75 0.75 -0.8 0.8 ns 14 tdqsq dq valid data delay time from dqs 0.5 0.6 ns thp clock half period tclmin or tchmin tclmin or tchmin ns tqh output dqs valid window thp-0.75 thp-1.0 ns tdqss write command to first dqs latching transition 0.75 1.25 0.75 1.25 tck tdqsh dqs input high level width 0.35 0.35 tck tdqsl dqs input low level width 0.35 0.35 tck tdss dqs falling edge to clk setup time 0.2 0.2 tck tdsh dqs falling edge hold time from clk 0.2 0.2 tck tmrd mode register set command cycle time 15 15 ns twpres write preamble setup time 0 0 ns 16 twpst write postamble 0.4 0.6 0.4 0.6 tck 15 twpre write preamble 0.25 0.25 tck tis input setup time (address and control) 0.9 1.1 ns 19 tih input hold time (address and control) 0.9 1.1 ns 19 trpst read postamble 0.4 0.6 0.4 0.6 tck trpre read preamble 0.9 1.1 0.9 1.1 tck -10 unit notes tck clk cycle time symbol ac characteristics parameter -75
mitsubishi electric - 19 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric ac timing requirements(continued) ( ta=0 ~ 70 o c, vdd = vddq = 2.5v + 0.2v, vss = vssq = 0v, unless otherwise noted) output load condition dq output timing measurement reference point v ref v ref dqs vref zo=50 w 30 pf 50 w vout vtt=vref min. max min. max tras row active time 45 120,000 50 120,000 ns trc row cycle time(operation) 65 70 ns trfc auto ref. to active/auto ref. command period 75 80 ns trcd row to column delay 20 20 ns trp row precharge time 20 20 ns trrd act to act delay time 15 15 ns twr write recovery time 15 15 ns tdal auto precharge write recovery + precharge time 35 35 ns twtr internal write to read command delay 1 1 tck txsnr exit self ref. to non-read command 75 80 ns txsrd exit self ref. to -read command 200 200 tck txpnr exit power down to command 1 1 tck txprd exit power down to -read command 1 1 tck 18 trefi average periodic refresh interval 7.8 7.8 m s 17 -10 unit notes symbol ac characteristics parameter -75 capacitance ( ta=0 ~ 70 o c, vdd = vddq = 2.5v + 0.2v, vss = vssq = 0v, unless otherwise noted) min. max. ci(a) input capacitance, address pin vi=1.25v 2.0 3.0 pf 11 ci(c) input capacitance, control pin f=100mhz 2.0 3.0 pf 11 ci(k) input capacitance, clk pin vi=25mvrms 2.0 3.0 0.25 pf 11 ci/o i/o capacitance, i/o, dqs, dm pin 4.0 5.0 0.50 pf 11 0.50 notes limits symbol parameter test condition unit delta cap.(max.)
mitsubishi electric - 20 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric notes 1. all voltages are referenced to vss . 2. tests for ac timing, idd, and electrical ac and dc characteri stics, may be conducted at nominal reference/supply voltage levels, however, the specifications and device operation s are guaranteed for the full voltage range specified. 3. ac timing and idd tests may use the vil to vih swing of up to 1.5v in the test environment. input timing is still referenced to vref (or to the crossing point for ck//ck), and pa rameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew ra te for the input signals is 1v/ns in the range between vil(ac) and vih(ac). 4. the ac and dc input level specifications are as defined in th e sstl_2 standard (i.e. the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above (below) the dc input low (high) level. 5. vref is expected to be equal to 0.5* vddq of the transmitting device, and to track variations in the dc l evel of the same. peak - to - peak noise on vref may not exceed + 2% of the dc value. 6. vtt is not applied directly to the device. vtt is a system su pply for signal termination resistors, is expected to be set equal to vref, and must track variations in the dc level of vref . 7. vid is the magnitude of the difference between the input leve l on clk and the input level on /clk. 8. the value of vix is expected to equal 0.5* vddq of the transmitting device and must track variations in the dc level of the same. 9. enables on - chip refresh and address counters. 10. idd specifications are tested after the device is properly i nitialized. 11. this parameter is sampled. vddq = 2.5v + 0.2v, vdd = 2.5v + 0.2v , f = 100 mhz, ta = 25 o c, vout(dc) = vddq /2, vout(peak to peak) = 25mv. dm inputs are grouped with i/o pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). 12. the clk//clk input reference level (for timing referenced to clk//clk) is the point at which clk and /clk cross; the input reference level for signals other than clk//clk, is vr ef. 13. inputs are not recognized as valid until vref stabilizes. ex ception: during the period before vref stabilizes, cke < 0.3vddq is recognized as low. 14. t hz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the dev ice output is no longer driving (hz), or begins driving (lz). 15. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 16. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this clk edge. a valid transition is defined as monotonic, and satisf ies the input slew rate specifications. when no writes were previously in progress on the bus, dqs will be transitioning from high - z to logic low. if a previous write was in progress, dqs could be high, low, or trans itioning from high to low at this time, depending on tdqss .
mitsubishi electric - 21 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric notes (continued) 17. a maximum of eight auto refresh commands can be asserted to any given ddr sdram device. 18. txprd should be 200 tclk when the clocks are unstable during the power down mode. 19. for command/address and ck & /ck slew rate > 1.0v/ns. 20. idd7 : operating current is measured under the conditions (1).four bank are being interleaved with trc (min),burst mode,address and control inputs on nop edge are not changing. iout = 0ma (2).timing patterns - ddr200( - 10) (100mhz,cl=2) : tck =10ns, cl=2, bl=4, trrd =2* tck , trcd =3* tck , read with autoprecharge setup:a0 n a1 r0 a2 r1 a3 r2 read :a0 r3 a1 r0 a2 r1 a3 r2 - repeat the same timing with random address changing 50% of data changing at every transfer - ddr266b( - 75) (133mhz,cl=2.5) : tck =7.5ns, cl=2.5, bl=4, trrd =2* tck , trcd =3* tck , read with autoprecharge setup:a0 n a1 r0 a2 r1 a3 r2 n r3 read :a0 n a1 r0 a2 r1 a3 r2 n r3 - repeat the same timing with random address changing 50% of data changing at every transfer - ddr266a( - 75a) (133mhz,cl=2) : tck =7.5ns, cl=2, bl=4, trrd =2* tck , trcd =3* tck , read with autoprecharge setup: a0 n a1 r0 a2 r1 a3 r2 n r3 read : a0 n a1 r0 a2 r1 a3 r2 n r3 - repeat the same timing with random address changing 50% of data changing at every transfer *legend: a=activate,r=read, p= precharge , n=nop
mitsubishi electric - 22 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric / clk dqs tis tih vref clk valid data read operation tac tdqsck tcl tch tck tdqsq tqh trpre trpst dqs / clk clk tdqss tds tdh tdqsl tdqsh twpre write operation / tdqss=max. tdss twpres twpst dqs / clk clk tdqss tds tdh tdqsl tdqsh twpre write operation / tdqss=min. tdsh twpres twpst dq dq dq cmd & add.
mitsubishi electric - 23 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric the ddr sdram has four independent banks. each bank is activate d by the act command with the bank addresses (ba0,1). a row is indicated by the row addres s a12 - 0. the minimum activation interval between banks is trrd. bank activate (act) operational description the pre command deactivates the bank indicated by ba0,1. when mu ltiple banks are active, the precharge all command (prea,pre+a10=h) is available to deactivat e all banks them at the same time. after trp from the precharge, an act command to the same bank can be issu ed. precharge (pre) bank activation and precharge all (bl=8, cl=2) a precharge command can be issued after bl/2 time from a read co mmand. precharge all command a0 - 9,11 - 12 a10 ba0,1 dq act xa xa 00 read y 0 00 act xb xb 01 pre trrd trcd 1 act xb xb 01 tras trp trcmin 2 act command / trcmin dqs qa0 bl/2 qa1 qa2 qa3 qa4 qa5 qa6 qa7 / clk clk
mitsubishi electric - 24 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric after trcd from the bank activation, a read command can be issue d. 1st output data is available after the /cas latency from the read, followed by (bl - 1) consecutive data. (bl:burst length) the start address is specified by a12 - a11,a9 - a0(x4)/a11,a9 - a0(x8), and the address sequence of burst data is defined by the burst type. a read command may be a pplied to any active bank, so the row precharge time (trp) can be hidden during the continuous burst data by interleaving the multiple banks. when a10 is high in read command, the auto - precharge (reada) is performed. any command(read,write,pre,act) asserted to the same bank is inh ibited till the internal precharge is completed. the internal precharge operation starts at bl/2 time after reada command. the next act command can be issued after (bl/2+trp) time from th e previous reada. read multi bank interleaving read (bl=8, cl=2) / clk command a0 - 9,11 - 12 a10 ba0,1 dq act xa xa 00 read y 0 00 read y 0 10 act xb xb 10 pre 0 00 trcd / cas latency burst length dqs qa0 clk qa1 qa2 qa3 qa4 qa5 qa6 qa7 qb0 qb1 qb2 qb3 qb4 qb5 qb7 qb8
mitsubishi electric - 25 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric trcd trp bl/2 bl/2 + trp read with auto - precharge (bl=8, cl=2,2.5) command a0 - 9,11 - 12 a10 ba0,1 dq act xa xa 00 read y 1 00 dqs / clk clk internal precharge starts here qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 dq dqs qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 cl=2 cl=2.5 0 1 2 3 4 5 6 7 8 9 10 11 12 operating description when new command is asserted. legal legal illegal illegal illegal illegal illegal illegal writea(cl=2.5) legal legal legal illegal illegal illegal illegal illegal write(cl=2) legal legal legal legal legal legal legal legal pcg legal legal legal legal legal legal legal legal act legal legal legal illegal illegal illegal illegal illegal writea(cl=2) legal legal illegal illegal illegal illegal illegal illegal write(cl=2.5) legal legal legal legal legal legal legal legal reada legal 10 legal 9 legal 8 legal 7 legal 6 legal 5 legal 4 3 legal read for different bank asserted command
mitsubishi electric - 26 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric after trcd time from the bank activation, a write command can be issued. 1st input data is sampled at the write command with data strobe input, followed by (bl - 1) data being written into ram. the burst length is bl. the start address is specified by a12 - a11,a9 - a0(x4)/a11,a9 - a0(x8), and the address sequence of burst data is defined by the burst type. a w rite command may be applied to any active bank, so the row precharge time (trp) can be hidden durin g the continuous input data by interleaving the multiple banks. the write recovery time ( twr ) is required from the last written data to the next pre command. when a10 is high in a write command, the a uto - precharge(writea) is performed. any command(read,write,pre,act) to the same bank is i nhibited till the internal precharge operation is completed. the next act command can be is sued after tdal from the last input data cycle. write multi bank interleaving write (bl=8) command a0 - 9,11 - 12 a10 ba0,1 dq act xa 00 write 00 write 0 0 10 act xb 10 0 10 trcd d trcd d pre xa 0 00 pre dqs / clk clk da0 da1 da2 da3 da4 da5 da6 da7 db0 db1 db2 db3 db4 db5 db6 db7 xa ya yb xb
mitsubishi electric - 27 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric write with auto - precharge (bl=8) command a0 - 9,11 - 12 a10 ba0,1 dq act xa 00 write 1 00 act xb 00 trc d da0 dqs / clk clk da1 da2 da3 da4 da5 da6 da7 tdal xa y xb 0 1 2 3 4 5 6 7 8 9 10 11 12 legal legal legal legal legal legal legal legal pcg legal legal legal legal legal legal legal legal act legal legal legal legal legal legal legal legal writea legal legal legal legal legal legal legal legal write legal legal legal illegal illegal illegal illegal illegal reada legal 10 legal 9 legal 8 illegal 7 illegal 6 illegal 5 illegal 4 3 illegal read for different bank asserted command operating description when new command is asserted.
mitsubishi electric - 28 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric burst interruption [ read interrupted by read] burst read operation can be interrupted by the new read command issued to any other bank. random column access is allowed. read to read interval is 1clk a s the minimum. read interrupted by read (bl=8, cl=2) command a0 - 9,11 - 12 a10 ba0,1 dq yi read read read read yj yk yl 0 0 0 0 00 10 00 01 dqs qai0 qai1 qaj0 qaj1 qaj2 qaj3 qak0 qak1 qak2 qak3 qak4 qak5 qal0 qal1 qal2 qal3 qal4 qal5 qal6 qal7 / clk clk [ read interrupted by precharge] burst read operation can be interrupted by precharge of the same bank. read to pre interval is 1 clk minimum. the time between pre command to output disable is equal to the cas latency. as a result, read to pre interval determines valid data length t o be outputed . the figure below shows the example of bl=8. read interrupted by precharge (bl=8) cl=2.5 command dqs command dq command dq q0 q1 q2 q3 q0 q1 / clk clk dq q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dqs
mitsubishi electric - 29 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric read interrupted by precharge (bl=8) cl=2.0 / clk clk command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dqs
mitsubishi electric - 30 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric burst read operation can be interrupted by a burst stop command( term). read to term interval is 1 clk minimum. the time between term command to output disabl e equal to the cas latency. as a result, read to term interval determines valid data length to be output. the figure below shows the example of bl=8. [ read interrupted by burst stop] read interrupted by term (bl=8) cl=2.5 command dqs command dq command dq q0 q1 q2 q3 q0 q1 / clk clk dq q0 q1 q2 q3 q4 q5 term read read term read term dqs dqs cl=2.0 command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 term read read term read term dqs dqs
mitsubishi electric - 31 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric [ read interrupted by write with term] read interrupted by term (bl=8) cl=2.5 command dq q0 q1 q2 q3 / clk clk read term dqs write d 0 d1 d2 d3 d4 d5 cl=2.0 command dq q0 q1 q2 q3 read term dqs write d0 d1 d2 d3 d4 d5 d6 d7
mitsubishi electric - 32 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric burst write operation can be interrupted by write to any bank. r andom column access is allowed. write to write interval is 1 clk minimum. [ write interrupted by write] [ write interrupted by read] burst write operation can be interrupted by read of the same or the other bank. random column access is allowed. internal write to read command interval(twtr) is 1 clk minimum. the input data masked by dm in the interrupted read cycle is "don't care". twtr is referenced from the first positive edge after the last data input. write interrupted by read (bl=8, cl=2.5) command a0 - 9,11 a10 ba0,1 dq write yi 0 00 read yj 0 00 dai0 dai1 qaj0 qaj1 qaj2 qaj3 qs qaj4 qaj5 qaj6 qaj7 dm twtr / clk clk write interrupted by write (bl=8) command a0 - 9,11 - 12 a10 ba0,1 write yi 0 00 write yk 0 10 write yj 0 00 write yl 0 00 dq dai1 daj1 daj3 dak1 dak3 dak5 dal1 dqs dal2 dal3 dal5 dal6 dal7 dal4 dal0 dak4 dak2 dak0 dai0 daj0 daj2 / clk clk
mitsubishi electric - 33 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric burst write operation can be interrupted by precharge of the sam e or all bank. random column access is allowed. twr is referenced from the first positive clk edge after the last data input. [ write interrupted by precharge] write interrupted by precharge (bl=8, cl=2.5) command a0 - 9,11 - 12 a10 ba0,1 dq write yi 0 00 pre 00 dai0 dai1 qs dm twr / clk clk
mitsubishi electric - 34 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric [ initialize and mode register sets] command / clk clk emrs pre nop mrs pre ar ar mrs act code code xa code xa 1 0 xa a0 - 9,11 - 12 a10 code 1 ba0,1 dqs dq 1 0 0 0 0 code tmrd tmrd trp trfc trfc tmrd mode register set, reset dll extended mode register set [ auto refresh] auto - refresh cycle is initiated with a refa(/cs=/ras=/cas=l,/we=cke=h ) command. the refresh address is generated internally. 8192 refa cycles wi thin 64 ms refresh 512 mbits memory cells. the auto - refresh is performed on 4 banks concurrently. before performing an auto refresh, all banks must be in the idle state. the minimum interv al between auto - refreshes is trfc . no command is allowed within trfc time after the refa command. auto - refresh / ras cke / cs / cas / we a0 - 12 ba0,1 nop or deselect trfc auto refresh on all banks auto refresh on all banks / clk clk cke initialize and mrs
mitsubishi electric - 35 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric [ self refresh] self - refresh mode is entered by asserting a refs command (/cs=/ras=/c as=l,/we=h,cke=l). the self - refresh mode is maintained as long as cke is kept low. during th e self - refresh mode, cke becomes asynchronous and the only enable input. all other inputs including clk are disabled and ignored to save the power consumption. in order to exit the self - refresh mode, the device shall be supplied the stable clk input, followed by desel or nop command, then asserting cke for the period longer than txsnr/txsrd. self - refresh / ras cke / cs / cas / we a0 - 12 ba0,1 txsnr self refresh exit / clk clk x y x y txsrd stable clk self refresh entry
mitsubishi electric - 36 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric the purpose of clk suspend is power down. cke is synchronous inp ut except during the self - refresh mode. a command at cycle is ignored. from cke=h to norma l function, dll recovery time is not required when the stable clk is supplied during the power down mode. [ power down] / clk clk power down by cke command pre cke command act cke standby power down nop nop valid nop nop valid active power down dm is defined as the data mask for write data. during the write s, dm masks the input data cycle by cycle. latency of dm to write mask is 0. [ dm control] dm function(bl=8,cl=2) command dqs dq dm write read d0 d1 d3 d4 d5 d6 d7 masked by dm=h don't care q2 q3 q4 q5 / clk clk q0 q1 q6 txpnr/txprd
mitsubishi electric - 37 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into mak ing semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due considerat ion to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxi liary circuits, (ii) use of non - flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials these materials are intended as a reference to assist our custo mers in the selection of the mitsubishi semiconductor product best suited to the customer ? s application; they do not convey any license under any intellec tual property rights, or any other rights, belonging to mitsubishi electric corporation o r a third party. mitsubishi electric corporation assumes no responsibility for a ny damage, or infringement of any third - party ? s rights, originating in the use of any product data, diagrams, charts, pr ograms, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authoriz ed mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed he rein. the information described here may contain technical inaccuracie s or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page ( http://www.mitsubishichips.com) . when using any or all of the information contained in these mat erials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electr ic corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at s take. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when con sidering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportati on, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation i s necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese e xport control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws an d regulations of japan and/or the country of destination is prohibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.
mitsubishi electric - 38 - m2s12d20/ 30tp - 75, - 75l, - 10, - 10l feb. '02 mitsubishi lsis ddr sdram (rev.1.1) 512 m double data rate synchronous dram mitsubishi electric revision history rev. 1.0 nov ? 01 - new registration rev. 1.1 jan ? 02 - added - 75l, - 10l spec. - added writea and reada operating description table when new comm and asserted - deleted - 75a spec. - added ac overshoot and overshoot spec. - changed the average supply current from vdd spec. limits(max.) -75 -10 x4 200 195 x8 205 200 x4 210 205 x8 215 210 x4 35 35 x8 40 40 x4 65 60 x8 70 65 x4 215 205 x8 225 215 x4 210 200 x8 220 210 idd5 x4/x8 360 340 idd6 x4/x8 6 6 x4 400 380 x8 410 390 x4/x8 idd2p idd2f idd0 idd1 symbol organization 35 20 20 35 idd7 idd4w x4/x8 idd3p idd4r idd3n from to -75 -10 140 130 140 130 150 140 160 150 30 25 30 25 15 12 45 35 45 35 190 140 220 170 180 150 210 180 idd5 280 260 idd6 6 6 -l 4 4 380 300 400 320 6 idd4r idd3n idd2p idd2f idd0 idd1 symbol ma unit limits(max.) idd7 idd4w idd3p 6

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